1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a combined gate and source/drain contact structure and the resulting semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits fabricated using MOS technology, field effect transistors (FETs—both NFETs and PFETs), such as planar field effect transistors and/or FinFET transistors, are provided that are typically operated in a switched mode, i.e., these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first lower end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end is connected to a respective metal line in the metallization layer by a conductive via. Such vertical contact structures are considered to be “device-level” contacts or simply “contacts” within the industry, as they contact the “device” that is formed in the silicon substrate. The contact structures may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. In other applications, the contact structures may be line-type features, e.g., source/drain contact structures.
FIG. 1 is a cross-sectional view of one illustrative embodiment of an integrated circuit product 10 comprised of a plurality of transistor devices formed in and above a semiconductor substrate 12. A schematically depicted isolation region 13 has also been formed in the substrate 12. In the depicted example, the transistor devices are comprised of an illustrative gate structure 14, i.e., a gate insulation layer 14A and a gate electrode 14B, a gate cap layer 16, a sidewall spacer 18 and simplistically depicted source/drain regions 20 (S/D). At the point of fabrication depicted in FIG. 1, a layer of insulating material 17A, 17B, i.e., the interlayer dielectric, has been formed above the product 10. Other layers of material, such as contact etch stop layers and the like, are not depicted in the attached drawings. Also depicted are illustrative source/drain contact structures 21 which include a combination of a so-called “trench silicide” (TS) structure 22 and a so-called “CA contact” structure 24. Also depicted is a gate contact structure 26 which is sometimes referred to as a “CB contact” structure. The CB contact 26 is formed so as to contact a portion of the gate electrode 14B of the gate structure 14. The source/drain contact structures 21 are typically formed as line-type structures that extend across the entire width or a significant portion of the active region in the gate-width direction of the transistor devices. In many applications, the CB contact 26 is positioned above the isolation region 13, relatively far away from the active region i.e., the CB contact 26 is not positioned above the active region defined in the substrate 12. Such an arrangement is required so as to avoid shorting between the CB contact 26 and the TS or CA structures because of the very small gate pitches employed on current-day products. Such a restriction limits many design opportunities and increases the spacing between adjacent active regions.
In one embodiment, the process flow of forming the TS structures 22, CA contacts 24 and CB contacts 26 may be as follows. After a first layer of insulating material 17A is deposited, TS openings are formed in the first layer of insulating material 17A that expose portions of underlying source/drain regions 20. Thereafter, a thin layer of a metal silicide is formed through the TS openings, followed by forming tungsten (not separately shown) on the metal silicide regions and performing a CMP process down to the top of the gate cap layer 16. Then, a second layer of insulating material 17B is deposited and contact openings for the CA contacts 24 are formed in the second layer of insulating material 17B that expose portions of the underlying tungsten metallization. Next, the opening for the CB contact 26 is formed in the second layer of insulating material 17B and through the gate cap layer 16 so as to expose a portion of the gate electrode 14B. Typically, the CB contact 26 is in the form of a round or square plug. Thereafter, the CA contacts 24 and the CB contact 26 are formed in their corresponding openings in the second layer of insulating material 17B by performing one or more common deposition and CMP process operations, using the second layer of insulating material 17B as a polish-stop layer to remove excess material positioned outside of the contact openings. The CA contacts 24 and CB contact 26 typically contain a uniform body of metal, e.g., tungsten, and may also include one or more metallic barrier layers (not shown) positioned between the uniform body of metal and the layer of insulating material 17B. The source/drain contact structures 21 (TS contacts 22, CA contacts 24) and the CB contact 26 are all considered to be device-level contacts within the industry.
Also depicted in FIG. 1 is the first metallization layer—the so-called M1 layer—of the multi-level metallization system for the product 10. A plurality of conductive vias—so-called V0 vias—are provided to establish electrical connection between the device-level contacts—CA contacts 24 and the CB contact 26—and the M1 layer. The M1 layer typically includes a plurality of metal lines that are routed as needed across the product 10. The M1 lines 30 and the V0 structures are typically comprised of copper, and they are formed in a layer of insulating material 19 using known damascene or dual-damascene techniques. Additional metallization layers (not shown) are formed above the M1 layer, e.g., M2/V1, M3/V2, etc. As depicted, the device-level contacts are all positioned at a level that is below the level of the V0 structures.
The various transistor devices that are formed for the product 10 must be electrically isolated from one another. Typically, this is accomplished by forming a trench in the substrate 12, such as the above-described trench 13, and filling the trench with an insulating material, such as silicon dioxide. However, the formation of such trenches consumes very valuable plot space on the substrate 12. Moreover, in some applications, such as those integrated circuit products employing FinFET transistor devices, as device sizes have decreased, and packing densities have increased, it is sometimes difficult to form the desired isolation region. To overcome such a problem, in some applications, device designers have adopted the approach of forming a “dummy” transistor between two adjacent functioning transistors, and tying the gate electrode of the dummy transistor to ground (or logical low voltage level), i.e., zero volts. This is what is referred to as gate “tie-down.” Tying the gate electrode of the dummy transistor to ground insures that the dummy transistor will always be in the off-state, i.e., the dummy transistor will never become operational or be turned “ON.” In such a configuration, the dummy transistor serves to isolate the two adjacent functional transistors.
However, as noted above, as device dimensions continue to shrink, the physical space between the edge of the CB contact 26 to the dummy gate electrode and the trench silicide regions 22 formed on the dummy transistor becomes very small, and may essentially be zero for advanced devices, especially when necessary process margins and potential misalignment errors are considered. This can be very problematic when such a dummy transistor arrangement is contemplated. One of the source/drain regions for the dummy transistor device will be tied to a logically high voltage level (VDD). Should the CB contact for the dummy gate electrode short to the trench silicide region that is tied to VDD, the dummy gate will turn “ON” and thus no longer perform its isolation function.
The present disclosure is directed to various methods of forming a combined gate and source/drain contact structure and the resulting semiconductor device that may avoid, or at least reduce, the effects of one or more of the problems identified above.